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bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

How do you configure the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?

I need help configuring the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?. I started out with the Rocketboards Pcie example (https://www.rocketboards.org/foswiki/Projects/Strat...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Configuring PCIe root port on Stratix 10 to allow the HPS to map an I/O BAR can be a complex process.

To be honest , I never try such deep before, but I can lay down some of the tips/suggestion for you to move on further.


  1. Modify the device tree: The device tree is used by the kernel to determine the system's hardware configuration. You can modify the device tree to map an IO space for the PCIe bridge. You can use the "ranges" property in the device tree to specify the base address and size of the I/O space. The "reg" property can be used to specify the base address and size of the memory space. Here's an example of what the device tree entry might look like:

pcie0: pcie@ffe201000 {

compatible = "pci-host-ecam-generic";

reg = <0x0 0xffe201000 0x0 0x1000>;

#address-cells = <3>;

#size-cells = <2>;

ranges = <0x81000000 0x0 0x00000000 0x00010000 0x00000000 0x00010000>,

<0x82000000 0x0 0x00000000 0x00010000 0x00000000 0x00010000>;

interrupts = <0 184 4>;

num-lanes = <8>;

max-functions = <8>;

dma-coherent;

status = "okay";

};

  1. Enable the I/O space in the PCIe root port configuration: In the Qsys Designer, you can enable the I/O space in the PCIe root port configuration. Under the "Root Port" tab, set the "I/O Space Enable" option to "Enabled".
  2. Verify that the PCIe bridge supports I/O space: Not all PCIe bridges support I/O space. You can verify that the PCIe bridge in your system supports I/O space by checking the device datasheet or manual. If the PCIe bridge does not support I/O space, you may need to use a different bridge that does support it.
  3. Check the PCIe endpoint configuration: The PCIe endpoint device (e.g. video card) must be configured to use the I/O space instead of memory space. This is usually done using the device's configuration registers. The configuration registers can be accessed using the "setpci" command in Linux.


Hope this is able to help.


Regards,

Wincent_Intel


bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

Thank you for the response. I've had the device tree side all worked out for a bit now, but its what you describe in 1) is what I am missing. There is no root port tab in Qsys Designer (yes, my type is set to Root Port, not Endpoint), and no checkbox anywhere for "I/O Space Enable". Ive been all over that GUI and I can't find it. There's no way a full implementation of a PCI root port IP doesn't include a way to make an IO space. How could they leave something like that out? There is an I/O space described in the documentation (ug_s10_pcie_avmm.pdf) called the CRA, but it appears to have a specific purpose for the driver, and not for creating an I/O space.

Could you please reach out to somebody who is intimately familiar with the PCIe IP?

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Which varient of Stratix 10 board you are testing on ? GX or SOC version ?

    Regards,

    Wincent_Intel

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      Just to confirm that the step is correct to enable the IO space.
      Can you please check and let me know if you still cannot get it ?

      1. Open the Quartus Prime software and open your project.

      2. Open the "Platform Designer" tool by clicking on "Tools" > "Platform Designer".

      3. In Platform Designer, click on "System" in the left-hand pane, and then click on the "System Info" tab.

      4. Under the "Address Spaces" section, find the "I/O" row and check if the "Enable" column is set to "Yes". If it is already set to "Yes", then I/O Space is already enabled.

      5. If the "Enable" column is set to "No", click on the pencil icon to edit the I/O address space.

      6. In the "Edit I/O Space" dialog box, check the "Enable I/O Space" box, and then click "OK".

      7. Save the Platform Designer design and exit.

      8. In Quartus Prime, recompile the project and program the FPGA with the updated design.

      Looking forward to hear back from you. Please let me know if you are unable to get the feature.
      Regards,

      Wincent_Intel