New Contributor
Frequent ContributorHi KMich2,
The Arria V HMC use dedicated I/O pins as data, address, command, control, clock, and ground pins for the SDRAM interface. I have highlighted the hard memory interface pin-out in YELLOW in attached pin-out excel file. Therefore, user shouldn’t be assigning hard memory interface DDR3 pin-out to other pin location anymore. Only dedicated pin-out is acceptable.
I suggest you to modified your design by removing all the pin location assignment for DDR3 IP and re-compile your project.
Hope this helps.
Thanks
Regards,
NAli1
New ContributorAnother question related to this table... How do we invoke the 'optional function' on a pin, for example the VREFB4DN0 on pin AA12. I understand this should be an externally supplied reference voltage for bank 4D at 1/2 the selected IO standard for the bank, but the pin also seems to serve as an IO pin. Do we need to configure the pin to use it as a voltage reference input?
Frequent ContributorHi KMich2,
Depending on your design, if you used verilog code then you can set the input pin in your RTL ( as shown in Figure 1) , re-compile the design ( compile at Analysis and Synthesis stage will do) and assign this PIN_AA12 as input in your Pin Planner (Figure 2). Then directly connect the VREF to this PIN_AA12. Make sure also the I/O standard is set accordingly with your design. What shown in Figure below is just an example for your reference. 😊
Figure 1:
Figure 2:
If you are using the Qsys, then set the input in Qsys.
Hope this helps.
Thanks
Regards,
NAli1
New ContributorOK, so I just need to assign the pin as an input and it will act as a reference for all the other pins on the bank? Thanks.
Frequent ContributorYes , you are right.
You are most welcome 😊
Regards,
NAli1
