Forum Discussion
Hi KMich2,
As per you said the device have 2 hard memory controllers (HMC), so I assume you are using Arria V GX A1 or A3 Device.
By right, both Bank 4 and 7 is usable for this device.
May I know what is the data width you used and what type of fitter error you seen?
Just for your reference, you may refer to this handbook (page 264) in below link to get more information on Hard Memory Controller in Arria V device.
https://www.intel.com/content/www/us/en/programmable/documentation/sam1403480004852.html#sam1403479856478
Regards,
NAli1
- KMich26 years ago
New Contributor
Hi,
The device I am using is 5AGXMA3D6F27C6.
The controller width is 32, the DQ bus is 16 bits.
The error messages I am getting are as follows:
Error (175006): Could not find path between the HPHY and destination pin
Info (175027): Destination: pin DDR3_CSn
Info (175015): The I/O pad DDR3_CSn is constrained to the location PIN_W13 due to: User Location Constraints (PIN_W13)
Info (14709): The constrained I/O pad is contained within this pin
Error (175022): The HPHY could not be placed in any location to satisfy its connectivity requirements
Info (175021): The pin was placed in location W13
Info (175029): 1 location affected
Info (175029): MEMPHY_X55_Y90_N1
I assume there must be a setting to make the device on bank 4 the master, but it's not clear what this setting should be or how to enter it, as there is no option to select the device in the UniPHY IP wizard, any advice?