How do I access the Intel® 'Cyclone V GX' DDR3 hard memory controller 'Configuration and Status Interface'?

Hi dlim,

Thank you for information about 'csr_clk' .

Please give me explanation about bits in control register 'CFG_AUTO_PCH_ENABLE'(address 0x069)

in 'Hard Controller Register Map'. I didn't found in documentation (External Memory Interface

Handbook Volume 3: Reference Material (Updated for Intel® Quartus® Prime Design Suite: 17.0))

the descriptions of this bits.

Thanks.

Regards,

VBotn