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I have a Linux driver that at least triggers some DMA transfer. I will post it online once I have the last issues worked out. I need some insights though, can someone look along at what I miss?
Table 7-13 on page 7-19 of PCIe UG 8.0:
82 DWORDS (32-bit words) are transferred by the End Point DMA engine from Root Complex (or BFM) memory from (bus) address 0x8EF0 to End Point memory address 0x3.
The table also specifies that "Data" is initialized with incrementing values in the address range 0x8900-0x8940.
But this address range is not used in the DMA transfer at all??!
What did I miss?
The same question applies to descriptor [1] and [2].
Second unclearity:
In the header, no control bits are set. In the descriptors, no control bits are set.
How then can the Root Complex (BFM) poll for EPLAST??! It is only updated if either EPLAST_ENA is set in the descriptor control bits or header control bits.
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Regarding the first issue, unfortunately it appears the User Guide documentation is out of sync with the actual altpcietb_bfm_driver_chaining.v descriptor setup. The Verilog localparam statements that define all of the WR_DESCxxx and RD_DESCxxx values are by definition the correct values.
I don't see the problem with the second issue. The first two times the "chained_dma_test" task is called, the input "use_eplast" is set to 1. Through some sub task calls we end up in task "dma_set_header" where "use_eplast" sets dt_dw0[18]. dt_dwo0 is then written to the descriptor header register in the Endpoint. Setting this bit in the EP register is what causes EPLAST to be updated during the DMA operation.
The next two calls to the "chained_dma_test" use MSI instead of updating EPLAST to report the status.
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