- You said: I have so many questions with the chaining dma example.I am wondering why Altera not release the source code of pcie software application such as altpcie_demo.exe.
You are correct, all of this confusion would be eliminated if they would release this source code (driver source might be needed as well). Do you think we need to start a new thread to explicitly ask for this?
- You said: I think the correct method is the software application writes Descriptor Table Header into Bar2(or3) mapped endpoint header descriptor registers at offset 0x00-0x1c.
After reading PCI Express Compiler Users Guide, I thought the same thing, but then I started looking at the bus function model (BFM) driver source code to see how a DMA simulation is performed, and now I think otherwise. For example, look at the file '
C:\altera\72\kits\ArriaGX_PCIe\Examples\PCIe_HighPerformanceDesign\Quartus\top_x4_examples\chaining_dma\testbench\altpcietb_bfm_driver_chaining.v' I believe this file is one of the higher level bfm driver routines. If you look at the file you can find the following (some parts omitted for brevity):
# #########BEGIN CODE################
// Run the chained DMA write
task dma_wr_test(...);
begin
// write 'write descriptor table in the RC Memory
dma_set_wr_desc_data(bar_table, setup_bar);
// Write Descriptor header in EP memory PRG
dma_set_header( ... )
end# #########END CODE################
If you look at the called functions dma_set_wr_desc_data() claims it writes the descriptor table in root complex (PC / host) memory.
Also, the comments above dma_set_header() function shows descriptor header tables for endpoint and root complex memory. The documentation almost reads like there is one descriptor header table mapped to a BAR 2. All in all, the code is not clear for porting to an actual implementation because I cant tell if shared memory means BFM driver memory or memory mapped by a BAR (or they are the same thing in an actual implemenation).
I wish there was a document that explained the reference design a little more for the vantage point of someone that wants to modify the existing design, and not from the BFM vantage point. The BFM blurs what needs to be done by a PC and what is contained in the reference design.
Best of luck, it appears we both need some right now. :cool:
Honored Contributor
