Forum Discussion
Occasional ContributorHIgh power consumption in LPDDR3 EMIF interface Arria 10
Solved: The gift that keeps on giving.
RREF_BL and RREF_TL, 2K resistor to ground.
Probably want to revise the docs to make this clearer to people who are not using the transceivers.
Occasional ContributorClearer statement of problem:
Device: 10AX022C3U19I2LG
Attached memory: MT52L256M32D1PF
Uses Bank 2J for mem_dq and mem_dqs/mem_dqs_n according to LPDDR3 scheme 1. Quartus validates.
Uses Bank 2K for control, address and reference clock (CLK_2K_1p/n), again using LPDDR3 scheme 1. Quartus validates.
Device operates under control of external ARM, and that interface works.
When the board starts, an unreasonable amount of power is consumed in the FPGA and it gets too hot to touch.
LPDDR3 calibration results both inactive.
When the EMIF section is held in reset by an ARM-controlled signal, the excess power stops.
We do not think this is a short as there is no damage to the board. Is there something we should check?
