Hi, I'm trying to make a delay instruction in verilog, I have an output (PWM) and I want to generate another output (PWM1) from PWM but with a delay: i tried this : assign #50 pwm1 = pwm; but it's not working best regards,

Hi,

In verilog '#' is not synthesizable so delays are useful for behavioral simulation in testbenches not in design. If you want to create delays in design that you can achieve using Flip flops & buffers. Single D-Flipflop will generate single clock cycle delay & you can generate multiple clock delays using counter.

Regards,

Vicky