Forum Discussion
Deshi_Intel
Regular Contributor
7 years agoHi JShel4,
Yes, it will auto down trained from 10G to 1G if link can't maintain at 10G.
I presume you are referring to CDR loose lock condition when you mentioned lock_to_data is toggling. This normally is caused by signal integrity concern.
You can refer to attached debug checklist to get some clue on where to debug. Although this debug checklist is created for Cyclone 10 FPGA but the debug flow is the same.
Thanks.
Regards,
dlim