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JShel4's avatar
JShel4
Icon for New Contributor rankNew Contributor
7 years ago

Help with 10G Ethernet Configuration

Newbie question on 10G Ethernet configuration. I have Arria 10 FPGA sitting between the SFP+ optical module and 10G backplane connector (i.e. SFP+ --> FPGA --> backplane). What is the easiest way f...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi JShel4,

It's fine to connect xgmii_rx_dc to xgmii_tx_dc. It should be able to recognize as both are Intel FPGA IP. The XCVR PHY user guide doc explanation is meant for connection to 3rd party IP that use xgmii_sdr_data/ctrl interface.

Can you traced the timing failure path is really constrained within KR PHY IP only. Then this is expected known issue that can be ignored as mentioned in XCVR PHY user guide doc. Refer to attached pic.

However, my recommendation is to always use latest Quartus version (for instance v18.1) to compile your design so that it contains all the latest issue bug fix.

Thanks.

Regards,

dlim

JShel4's avatar
JShel4
Icon for New Contributor rankNew Contributor
7 years ago

Thanks Dlim! I am using version 18.1 Pro on Linux. It seems that Intel/Altera IP is not fully battle tested. I also see Big timing violations when using the clocking scheme recommended in the PHY user guide and AN795 - specifically when getting XGMII clock from separate FPLL to clock the registers interfacing with the XGMII tx and rx paths of the 1g/10g phy.

One question: Does the 1G/10G PHY auto down-train from 10G to 1G? I am seeing the following behavior in my bring-up. Please let me know if you have any thoughts on this:

  1. The 1G/10G PHY (not KR), establishes the link successfully when connected to a Netgear 1G switch - using a SFP+ cable
  2. However, it does not link - up when connecting to a 10G Netgear switch using the SFP+ cable. In this case, the lock-to-data never stays high - it keeps toggling or loosing the lock.

Please let me know what you think. Appreciate all your thoughts/help!