New Contributor
Regular ContributorHi JShel4,
If you don't care about MAC functionality and processing then you can just use Arria 10 FPGA Ethernet PHY IP like "1G/10GbE and 10GBASE-KR PHY" IP to intercept your incoming data traffic from SFP module and retransmit the XGMII data to another Ethernet PHY IP and then blast out to your backplane.
KR option is available to support feature like "auto negotiation" and "link-training" in case you need it.
Thanks.
Regards,
dlim
New ContributorHello dlim, thank you for the quick response. I think I understood your point. Please help verify my implementation:
I am attaching two pictures towards the end of this reply --- showing the data paths --- XGMII (for 10G) and GMII (for 1G).
Logically, my Ethernet PHYs look something like this: SFP+ --> 1G/10G Phy --> KR PHY --> Backplane connector
Question: Do you see any issues in the data path - especially for XGMII ... do I need to re-wire for SDR XGMII? (like the table shown in page 137 of the Transceiver User Guide)?
One more question: Any suggestion on how to close timing inside the KR IP? I see timing violations in and around the AN block. For e.g. :
From Node: phys|kr_phy|xcvr_10gkr_a10_0|CHANNEL|rx_parallel_data_native[26]
To Node: phys|kr_phy|xcvr_10gkr_a10_0|CHANNEL|AN_GEN.AUTO_NEG|DECODE|dme_dly2[26]
Launch Clock: phys|kr_phy|xcvr_10gkr_a10_0|rx_pma_div_clk
Latch Clock: phys|kr_phy|xcvr_10gkr_a10_0|rx_pma_div_clk
Data Arrival Time: 15.434
Data Required Time: 13.897
Slack -1.537 (VIOLATED)Screen Shots of the GMII and XGMII data paths between the two PHYs
