Help: Windows didn't assign Bar0 to PCie (address mapping is not correct)

Hi Nial,

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This doesn't meet timing (with a pcie core clock to pcie core clock path setup failure), although the PCIe user guide says this configuration should

work in all '7 devices.

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I've updated the PDF and zip file linked to in the original thread:

http://www.alteraforum.com/forum/showthread.php?p=147114

I edited the C4GXSK constraints.tcl script to use a -7 speed grade, and I can confirm that timing fails for that speed grade. I agree that this is inconsistent with the PCIe Compiler Users Guide. I still can't get the Stratix IV GX x8 design to meet timing either.

Cheers,

Dave