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The Cyclone IV GX designs meet timing if you turn on multi-corner timing analysis.
Cheers,
Dave
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I need to reply about this in that other thread but I have a design which is...
CycloneIV '7
Hard IP PCIe core
Avalon MM interface with Qsys design flow
A fair bit of custom logic, but a fairly simple Avalon interface
My logic drives DMA to the host memory using the address translation tables as above
125MHz core clock.
This doesn't meet timing (with a pcie core clock to pcie core clock path setup failure), although the PCIe user guide says this configuration should work in all '7 devices.
I raised an SR but a project archive doesn't include the *.qsys file, and as whoever handled the SR couldn't open the qsys project they simply marked the SR as closed. :eek:
I don't actually need the 125Mhz clock so am using the 62.5MHz option but could have had my fingers burnt here.
Nial.
Honored Contributor
