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Honored Contributor
Honored ContributorHelp: Windows didn't assign Bar0 to PCie (address mapping is not correct)
Dear all, We changed the Altera Cyclone PCIe DDR2 reference design to our needs. However, it doesn't work. The address mapping is not correct, it doesn't agree to address assignments in Qsys. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Dave, p8 of which document? I can not find your information in page 1-8 of ug_pci_express.pdf --- Quote End --- Wrong document. Earlier in this discussion I directed you to read the document I posted in this thread: http://www.alteraforum.com/forum/showthread.php?t=35678 The Cyclone IV GX designs meet timing if you turn on multi-corner timing analysis. I'm still working through an Altera SR to get the Stratix IV GX design to meet timing. Cheers, Dave
