Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp: Windows didn't assign Bar0 to PCie (address mapping is not correct)
Dear all, We changed the Altera Cyclone PCIe DDR2 reference design to our needs. However, it doesn't work. The address mapping is not correct, it doesn't agree to address assignments in Qsys. ...
Altera_ForumHonored Contributor
Honored ContributorDave, p8 of which document? I can not find your information in page 1-8 of ug_pci_express.pdf
Thank you very much! --- Quote Start --- Its part of the PCIe core configuration. The core gets configured with two 1MB outgoing translation windows, eg., see p8. This window can be used to access any location in the PCIe address map. Using the Qsys DMA controller, you can access two 1MB regions of the host memory. This is not as flexible as a Qsys-to-PCIe bridge with a DMA controller embedded inside it, however, since that component does not exist, you need to figure out whether you can live with the existing solution. Cheers, Dave --- Quote End ---
