Help: Windows didn't assign Bar0 to PCie (address mapping is not correct)

Dave,

The data rate is high, DDR2 SDRAM is necessary to storage large temporary data to ensure real-time, and it is designed by my supervisor, not me.

My task is to make both DDR2 and on-chip memory work, not to avoid the problem by getting rid of DDR2 SDRAM or on-chip memory.

Could you tell me where is the link of your example ?

" in the Qsys PCIe example I sent a link to, the PCIe bridge can be configured with a 1MB outgoing translation window."

Thank you very much!

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Ok.

Why use the DDR memory for this? It would make more sense to me to use on-chip memory for parameters that the DSP logic will be using. Of course, that assumes there are a few parameters.

That data should be going directly into the DSP logic. What actually needs to be stored in the DDR? A power spectrum? A cross-correlation?

Again, this likely should go to on-chip RAM and registers.

You will never want to use the host CPU to transfer anything but a few simple parameters. The performance of a CPU issuing a write or read command to a PCIe device is slow. Its fine for setting up a few registers, or initializing a DMA controller, but its ultimately just slow.

You need to talk to a device driver developer. They will explain that devices that transfer data, eg., network cards, video cards, data processing cards, do not use the CPU for moving the data, they use a DMA controller on each of those respective cards.

You should design the hardware to match the requirements of the device driver developer.

30 frames per second of what? An HD image, or a 1024-point power spectrum? This data defines your sustained data rate from your board to the CPU. Calculate it. This is your design target!!!

If your data rate is low, perhaps a simple CPU-based read of that data will be sufficient. However, in most applications it would not be, or it would be a waste of CPU time, and DMA will be your only option. If you do need DMA, then you can discuss with your device driver developer whether or not the Altera DMA controller has sufficient functionality for your requirements.

For example, in the Qsys PCIe example I sent a link to, the PCIe bridge can be configured with a 1MB outgoing translation window. If your device driver developer can guarantee that the host data used for DMA is located in a single 1MB region, then you can just use that DMA controller directly.

Cheers,

Dave

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