Help: Windows didn't assign Bar0 to PCie (address mapping is not correct)

1) It is Cyclone IV GX speed grade 7, I modified the design in

http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs

changed the DDR2 to our 128 M 16 bit DDR2 SDRAM.

2) The memory is to be used for storing some parameters/commands for signal processing

3) There is a lot of RF data from ADCs for the FPGA to process, CPU needs to send commands/parameters, also obtains processed data storage in DDR2 SDRAM from PCIe. I don't know if CPU needs to see that memory or not, if it does not need to see that memory, how to realize ? to get the data from DDR2 SDRAM?

4) FPGA processes the ADC data,CPU sends commands/parameters, access data in on-chip memory or in DDR2 SDRAM. displays processed data for real-time (30frams/s) images on screen.

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That tells me what the hardware is, but it does not tell me anything about why. Here's a few questions;

1) What FPGA do you have on the board?

2) Why does the FPGA have memory? What is it to be used for?

3) Why does the host CPU need to see that memory?

4) What is your data flow?

For example, in my application I have high-speed ADCs and signal processing logic in the FPGA. The FPGA results will be written to DDR3 RAM, and then those results DMAed to the host CPU. There is a few MB of data that needs to be transferred every ~20ms. However, those results can be queued, and transferred as a larger DMA transfer every 500ms.

The host CPU will run Linux, and a device driver will setup the DMA controllers on multiple boards to DMA their results into main memory. The main memory will contain scatter-gather DMA buffers. The data will be moved out of the buffers once the host has processed the results.

You need to come up with a similar data flow description for your system.

Cheers,

Dave

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