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We have a PCIe Hard IP, 128M 16 bit DDR2 SDRAM and 21K 64-bit on-chip memory.
Qsys assigns 256MB for the DDR2 SDRAM due to Avalon MM interface, plus on-chip memory, the total size of Bar0 exceeds 256 MB, and we can not make it work with WinDriver and our computer (Windows XP).
It seems the maximum size of Bar0 for our computer is 256 MB.
So we want to make both DDR2 SDRAM and on-chip memory working, we want to reduce the size of Bar0.
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That tells me what the hardware is, but it does not tell me anything about
why. Here's a few questions;
1) What FPGA do you have on the board?
2) Why does the FPGA have memory? What is it to be used for?
3) Why does the host CPU need to see that memory?
4) What is your data flow?
For example, in my application I have high-speed ADCs and signal processing logic in the FPGA. The FPGA results will be written to DDR3 RAM, and then those results DMAed to the host CPU. There is a few MB of data that needs to be transferred every ~20ms. However, those results can be queued, and transferred as a larger DMA transfer every 500ms.
The host CPU will run Linux, and a device driver will setup the DMA controllers on multiple boards to DMA their results into main memory. The main memory will contain scatter-gather DMA buffers. The data will be moved out of the buffers once the host has processed the results.
You need to come up with a similar data flow description for your system.
Cheers,
Dave
Honored Contributor
