Help: Windows didn't assign Bar0 to PCie (address mapping is not correct)

Thank you, Dave.

We have a PCIe Hard IP, 128M 16 bit DDR2 SDRAM and 21K 64-bit on-chip memory.

Qsys assigns 256MB for the DDR2 SDRAM due to Avalon MM interface, plus on-chip memory, the total size of Bar0 exceeds 256 MB, and we can not make it work with WinDriver and our computer (Windows XP).

It seems the maximum size of Bar0 for our computer is 256 MB.

So we want to make both DDR2 SDRAM and on-chip memory working, we want to reduce the size of Bar0.

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I'm investigating the Altera IP at the moment:

http://www.alteraforum.com/forum/showthread.php?t=35678

The existing Qsys component does not implement a DMA controller as part of the bridge, so it does not meet the requirements for what I would consider to be a decent bridge. I need to complete the MegaWizard flow review and then some of the SOPC components on the Altera wiki. If none of them have features that meet my requirements, I'll create a design. I'll then document it and post it to the Altera wiki. I'm currently working on a board design, so might not get started on the bridge design for a little while (since it does not impact the board layout, just the resources used in the FPGA).

What exactly are the requirements of your design? Perhaps I or someone else on the forum can suggest a solution that will get you working now.

Cheers,

Dave

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