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Honored Contributor
Honored ContributorHelp: Windows didn't assign Bar0 to PCie (address mapping is not correct)
Dear all, We changed the Altera Cyclone PCIe DDR2 reference design to our needs. However, it doesn't work. The address mapping is not correct, it doesn't agree to address assignments in Qsys. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- How to have a "Qsys PCIe bridge"? because I can not find it in Qsys component library. what is the exact name? or do we need to build one ourselves? --- Quote End --- I'm investigating the Altera IP at the moment: http://www.alteraforum.com/forum/showthread.php?t=35678 The existing Qsys component does not implement a DMA controller as part of the bridge, so it does not meet the requirements for what I would consider to be a decent bridge. I need to complete the MegaWizard flow review and then some of the SOPC components on the Altera wiki. If none of them have features that meet my requirements, I'll create a design. I'll then document it and post it to the Altera wiki. I'm currently working on a board design, so might not get started on the bridge design for a little while (since it does not impact the board layout, just the resources used in the FPGA). What exactly are the requirements of your design? Perhaps I or someone else on the forum can suggest a solution that will get you working now. Cheers, Dave
