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Do you mean DDR2 is not connected to PCIe Hard IP, it is only connected to DMA?
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DDR2 and DMA and the Qsys PCIe bridge would be connected to a Qsys system. However, its the operation of a PCIe-to-Qsys bridge that you need to understand.
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What is the differences between PCIe address and Avalon address? Isn't PCIe address also Avalon address since it often uses Avalon MM interface?
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No, PCIe addresses and Qsys addresses are two completely separate address maps.
Consider the case of 4 identical FPGA boards plugged into a motherboard. Those four boards could be configured with identical Qsys systems, right? Their Qsys address maps are therefore identical. How can the PCIe address map be identical to the Qsys address map? It cannot.
In this case, how would each of the boards DMA into x86 memory? Well, the host would access each of the board's DMA controllers via registers mapped into a BAR. Each board would be uniquely mapped into the x86 address map by the BIOS. The Qsys source address on each board could be identical, but the PCIe destination address would be unique to each board.
Draw a picture of the address maps, and you'll see that a DMA controller is really a 'bridge' that can see the Qsys address map on one side, and the PCIe address map on the other.
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Also, do you have examples/more detailed documents about this?
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No. This is pretty standard for PCI development. However, its not exactly documented anywhere, its more like "that is just the way it is". Once you understand it, it makes sense.
Read the data sheet of the PLX PCI9054 PCI bridge, or read the PCI section of the Freescale MPC8349EA PowerQuicc II Pro processor documentation, and you'll see very similar descriptions of the operation of the PCI bridges.
Cheers,
Dave
Honored Contributor
