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Altera_Forum
Honored Contributor
14 years agoHelp: Windows didn't assign Bar0 to PCie (address mapping is not correct)
Dear all, We changed the Altera Cyclone PCIe DDR2 reference design to our needs. However, it doesn't work. The address mapping is not correct, it doesn't agree to address assignments in Qsys. ...
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- but will it reduce BAR0 size? I just concern if my computer can boot. Do you mean using DMA can reduce BAR0 size if the x86 host memory is still connected to Qsys ? --- Quote End --- The BAR size will be reduced to whatever the common set of control registers requires. Consider the following simple case. Lets say I have a DMA controller that has the following registers; 64-bit PCIe address, 32-bit Avalon (Qsys) address, direction (PCIe-to-Avalon or Avalon-to-PCIe), length in bytes, a control register and a status register. You need 7 32-bit registers to describe this. The minimum practical BAR size is about 256-bytes, but its more typical to use a page of the host memory, i.e., 4kB or 8kB. You can program the DMA controller to move a block of data to or from any PCIe address (which includes the host memory) to an Avalon address, which includes your DDR memory. Note how the host does not need to see the Avalon DDR memory, it is the DMA controller that needs to see those addresses. Cheers, Dave