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Honored Contributor
Honored ContributorHelp: Windows didn't assign Bar0 to PCie (address mapping is not correct)
Dear all, We changed the Altera Cyclone PCIe DDR2 reference design to our needs. However, it doesn't work. The address mapping is not correct, it doesn't agree to address assignments in Qsys. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Could you diagnose this problem? --- Quote End --- Go through the tutorial I wrote in the thread I pointed you to. The examples in the document are for x8 and x1, and there is a x4 PCIe in the example code. The boards are the Stratix IV GX Development kit and the Cyclone IV GX Transceiver Starter kit. There's enough detail in there for you to create a design for your specific board. Under code/pci_debug is a tool for accessing the BARs under Linux. You can use it to read/write to the on-chip RAM, and then later, when you add a DDR controller to the design, use it for accessing DDR. Cheers, Dave
