simonmartin
New Contributor
New ContributorHelp understanding AXI back pressure in timing diagram (user guide error?)
I am referring to the AXI Write timing diagrams (Figure 92 / 93) in the "Embedded Peripherals IP User Guide" on p. 331.
I believe there is a confusion between the **VALID and **READY signal usage ...
Hi Simon,
You are correct that in the AXI protocol, back pressure is indicated by the slave to the master using the ready signals, and not the valid signals. So, in both Figure 92 and Figure 93, the direction of the ready signals is seem to be incorrect. The s1_wready signal should be used to indicate back pressure in Figure 92, and the s1_bvalid signal should be used to indicate back pressure in Figure 93.
It seems like there might be an error in the timing diagrams which I will file a documentation enhancement. Thank you for bringing this to attention.
