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simonmartin's avatar
simonmartin
Icon for New Contributor rankNew Contributor
3 years ago
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Help understanding AXI back pressure in timing diagram (user guide error?)

I am referring to the AXI Write timing diagrams (Figure 92 / 93) in the "Embedded Peripherals IP User Guide" on p. 331. I believe there is a confusion between the **VALID and **READY signal usage ...
  • SyafieqS's avatar
    SyafieqS
    3 years ago

    Hi Simon,


    You are correct that in the AXI protocol, back pressure is indicated by the slave to the master using the ready signals, and not the valid signals. So, in both Figure 92 and Figure 93, the direction of the ready signals is seem to be incorrect. The s1_wready signal should be used to indicate back pressure in Figure 92, and the s1_bvalid signal should be used to indicate back pressure in Figure 93.

    It seems like there might be an error in the timing diagrams which I will file a documentation enhancement. Thank you for bringing this to attention.


SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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