Help! Implenting a Cmex S-functions into your FPGA

Oh thanks Dabuk, I have read the section 15 times LOL.

But I will send you my MDL files hopefully you can tell me where i am going wrong.

It simulates fine and as as converts it to VHDL but it fails on Synth and fitting.

The following error is shown in the DSP Report file :

Convert Mdl to VHDL : PASSED

Synthesis : FAILED Timestwo.map.rpt

Quartus II Fitter : ---------

Quartus II Map Log

Info (10544): VHDL Assertion Statement information at Timestwo.vhd(71): assertion "" DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 6.0"" is always false

Info: Elaborating entity "SBF" for hierarchy "SBF:Outputi"

Info: Elaborating entity "sAltrPropagate" for hierarchy "SBF:Outputi|sAltrPropagate:u0"

Error: Node instance "timetwoi" instantiates undefined entity "timetwo" File: C:/Nadeem_work/Matlab Tutorial/TimesTwo/Timestwo.vhd Line: 105

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning

Info: Allocated 135 megabytes of memory during processing

Error: Processing ended: Wed Feb 20 11:42:24 2008

Error: Elapsed time: 00:00:01

I have Attatched the following:-

Timestwo.mdl --- the simulink model file

Timestwo.VHD -- the top level entity file used to creat subsystem builder black box

timestwoc.txt-- is the s-function. this file has to be renamed to timestwo.c.

I realy appreciate you time and look forward to hear from you soon .

regards