Help! Implenting a Cmex S-functions into your FPGA

I'm really no expert on VHDL, so hopefully someone else can chime if I get anything wrong here.

The file you specify here should contain all the HDL necessary to synthesize the block. So I assume it will need the architecture. (It is possible to have your black box use more than one VHDL file, but it requires creating tcl scripts to compile those files in Quartus and ModelSim).

Not sure what you mean by last comment. DSP Builder will wire up the signals since it knows the names of the ports/clock/reset of your entity. If you mean internally in your entity, well then that kinds of up to you... :)

Hope that helps