Forum Discussion
JJame30
New Contributor
New ContributorHello, "# Fatal error in Process MEMORY at C:/altera/12.1/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39940". how to proceed? can you suggest a proper way to simulate my top level vhdl code?
I am working on interfacing Stratix 4 GX FPGA with DDR2. I used uniphy ip core in Megawizardpulgin tool. I got full files and i simulated example design with provided testbench (in modelsim). its wo...
KennyT_altera
Super Contributor
Super ContributorWhat steps that you had use to simulate your DDR2?
Here is the steps for simulation DDR2 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_debug.pdf
