Forum Discussion
ContributorHDMI Reference Design FR_CLK
HI Johnson,
On 2nd thought, I think you can still connect fr_clk while providing whatever clk frequency that's available on your board. Eg : 100MHz.
I found out more info. It should still works as stated from below A10 HDMI example design guideline doc that explained on fr_clk functionality.
- Free running clock (625 MHz) for primary transceiver reference clock. This clock is required for transceiver calibration during power-up state. This clock can be of any frequency.
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-hdmi-de.pdf
Thanks.
Regards,
dlim
Regular ContributorHi,
fr_clk is the transceiver power on calibration pll refclk source for HDMI Tx and CDR refclk0 for HDMI Rx.
It's recommended to follow back example design to use 300MHz.
Thanks.
Regards,
dlim
ContributorHi dlim.
Thank you for the reply!
What bothers me is the clock did not exist in the old reference design..
And I have a design following the old without this fr_clk..
And it's not possible to add this as all the clock pins are used.
Therefore would you check if this fr_clk is a must?
BRs,
Johnson
