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YBilg's avatar
YBilg
Icon for New Contributor rankNew Contributor
5 years ago
Solved

HDMI IP Example Design On Arria 10 SoC Development Kit

Hello, I am working on HDMI IP with Arria 10 SoC Development Kit. I have impelented the example design with the help of HDMI IP Example Design User Guide in Quartus 18.1. When I run the FPGA and N...
  • YBilg's avatar
    YBilg
    5 years ago

    Hi @Deshi_Intel ,

    We have finally solved the problem by supporting auxiliary in qsys user interface of HDMI IP and generating the .sof file again.

    Thank you for your support.

    Regards,

    Yıldız

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


May I know are you using exact HDMI Rx to Tx retransmit example design or your own modified HDMI design ?


The original A10 HDMI Rx to Tx retransmit example design is meant for A10 GX dev kit board, not A10 SOC dev kit board. So, I am not sure whether all the pin mapping is done correctly on A10 SOC dev kit board or not.


If possible, pls try out on A10 GX dev kit board to validate your hardware setup first.


Thanks.


Regards,

dlim


YBilg's avatar
YBilg
Icon for New Contributor rankNew Contributor
5 years ago

Hi @Deshi_Intel ,

I know that the A10 HDMI Rx to Tx retransmit example design is meant for A10 GX dev kit board, but it can be generated for other boards too. So, we did the pin mapping and esc. very carefully.

Since we completed the RX part successfully but we couldn't be able to success on the TX part; we have generated our own TX design and removed the RX and Nios parts. We just tried to display the test pattern which is generated by the test pattern generator in the simulation files. But we couldn't boot up the IP neither in FPGA nor in simulation. After 14 clocks of the resetting situation of the HDMI_TX IP, it just generates the constant values that I have described above. Unless we set the Scrambler_enable signal to high, it does not generates any outputs.

Regards,

Yıldız