Forum Discussion
ContributorHDMI IP -> DRMI (Dynamic Range Mastering InfoFrame) -> how to derive?
You are referring to the Design Example for Arria 10, but I'm working with the Cyclone-10.
Instructions for Cyclone 10 DRMI Filtering are different:
but they are not compatible with the generated code...
The User Guide for Arria 10, which you are referring to, is compatible to the generated code, which I have in my project...
Anyway, I'll set the multiplexer_in0_valid signal to '0' according to your recommendation and let you know whether it works.
Frequent ContributorHi amildm,
Good day.
DRMI packets are part of the Auxiliary data. These data is place in packets and transferred using 3 main data channel.
HDMI Video Stream Data
The reason that you are getting a constant value could be due to filtering mode.
In this case, when your source is transmitting the payload, the Aux packet filter the payload, and use the payload generated by the Aux packet generator.
Rx-Tx Link with DRMI
There is a way to disable this filter as shown in picture below:
Disabling HDR Insertion and Filtering
You may refer to below link for more information on said above:
HDMI Intel® FPGA IP User Guide - HDMI Overview
May I know what FPGA device are you using for your project?
Thank you.
Best Regards,
ZulsyafiqH_Intel
ContributorZulsyafiqH_Intel, thanks a lot for your your response!
I'll try to deal with the Design Example for HDR, will let you know how it's going.
My project is based on the Cyclon-10 GX device, Quartus Pro v19.3.
Thanks!
