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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
12 months ago
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HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support,

When creating a design with "HDMI Intel FPGA IP" having significant values as:
- Direction: Receiver
- Enable Active Video Protocol: AXIS-VVP Full
- Support FRL: Untick (disabled)

Then Quartus 24.3 Pro Build 212 (newest) fails in Analysis & Synthesis with the errors:

Error(13224): Verilog HDL or VHDL error at hdmi_rx_core_altera_hdmi_1975_ozylggi.v(771): index 2 is out of range [1:0] for 'cv_vid_de'
Error: Failed to elaborate design:
Error: Flow failed: Errors generated during elaboration
Error: Quartus Prime Synthesis was unsuccessful. 3 errors, 0 warnings

Archived project is attached.

Question: Is there any known fix or workaround for this problem?

Regards
M_DK_FPGA

PS. It appears that an internal non-designer assigned value PIXELS_PER_CLOCK is assigned to 8, as for FRL enabled, thus causing an internal loop to go out of range.

Video
  • Wincent_Altera's avatar
    Wincent_Altera
    9 months ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera

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  • M_DK_FPGA's avatar
    M_DK_FPGA
    Icon for Occasional Contributor rankOccasional Contributor
    12 months ago

    Hi Rong,

    Thanks for your answer, and for looking into this.

    As I understand the answer, then in order to use AXIS-VVP Full for video output protocol of an HDMI Sink (RX) core, it is required to use FRL = 1. The documentation for this is apparently in the description for parameter "Video in and out use the same clock"; a parameter that is unrelated to the parameter "Enable active video protocol" that assigns the video output protocol. As reference I have attached the PDF page where the figure in the answer is shown.

    But doc "HDMI Intel FPGA IP User Guide" version 2023.12.04 page 17 "Table 7. HDMI Intel FPGA IP Resource Utilization" describes that AXIS is supported for FRL = 0, as shown in image below, and in attached PDF page.

    Also, the HDMI PHY document "HDMI PHY Intel FPGA IP User Guide" version 2022.10.31 page 6 bottom, it requires FRL = 0 and AXIS enabled for our Arria 10 design, in order to use Intel HDMI TX or RX PHY IP, as shown in image below, and in attached PDF page.

    So, if use of AXIS in the HDMI RX core requires that FRL = 1, the consequence is that HDMI RX PHY can't be used, according to the PHY documentation. Otherwise, if AXIS is not used in the HDMI RX core, then the HDMI RX PHY can't be used either. For Arria 10, it means that HDMI RX PHY can't be used in any case.

    As an additional comment, then using FRL = 1 in the HDMI RX core will make the HDMI RX core more than 5 times larger, in a HDMI 2.0 design that does not require FRL.

    The contradicting documentation parts referenced above, and the out of place note in the parameter description, makes me uncertain about what is actually supported in the HDMI RX core.

    Question: Can you please revisit this question, based on the above information, and clarify what is actually supported, and what part of the documentation that is incorrect.

    Regards,

    M_DK_FPGA