Can you compile your VHDL file in Quartus II without using DSP Builder? (If not then there's little hope that HDL Import would do any better - it has to call Quartus).
Looks to me like you're instantiating an altsyncram with an invalid configuration for the device you've selected. Your best bet would be to read the manual/help for altsyncram.
If you actually intend to target the Stratix device family, you will have to change your VHDL. If you don't, then you should use the Signal Compiler block to set a different device family.