Honored Contributor
Honored ContributorI should point out that I had originally started development with a TPG inserted in the system in place of the CVI until we received an HD SDI camera. That worked fine, but I assume the TPG responded to the backpressure without overflowing like the CVI, so the effective frame rate was likely lower than 30fps. I have not confirmed this in SignalSpy, though.
I attempted to simulate the design, but the transceiver models apparently don't simulate the dynamic reconfiguration properly. I see the dynamic reconfiguration complete, but as soon as the transceiver requests reconfiguration, the PLL loses lock and the recovered clock stops transitioning (as expected). However, after reconfiguration has completed, the transceiver fails to lock to the incoming signal and the recovered clock never starts back up. I submitted a service request but the response was "i regret that the reference design is just used to show the capability of the products. we don't provide the support if customer want to run the rtl simulation in modelsim.
i hope you could understand.
thank you and have a nice day." Seriously? :confused:
