Forum Discussion

rsing108's avatar
rsing108
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

HBM2 interfacing with the PCI express hard IP STRATIX 10 MX

Hi, I am trying to interface HBM2 with pci express hard ip+ on stratix 10 MX. I am referencing to this example design https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/pci-express-gen3-x16-a...
  • BoonT_Intel's avatar
    BoonT_Intel
    5 years ago

    Hi, Sorry for the mistake.

    I tried the same and I only can see the 16bits on the address. These address bits are affected by the setting of "Address width of bursting master" of the PCIe IP. I believe the developer hack the IP and change the address width to 30 instead.

    If you need, you can change this by modifying the g3x16_hbm2_avmm_bridge_512_0.ip file.

    Search for Address width of Bursting Master and you can change the value to 30.


BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

I thought the AN881 is already a multiple BAR design?

It can access DDR4 and HBM2.

BAR 2 for HBM2 and BAR4 for DDR4.

By the way, you can check the design store and see if any design meet your needs - https://fpgacloud.intel.com/devstore/

Thanks.


  • rsing108's avatar
    rsing108
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi @BoonT_Intel ,

    A881 in the documentation uses multiple bars but the link to reference design is broken. The reference design I mentioned earlier uses only 1 bar i.e. for HBM.

    Thanks