Forum Discussion
Occasional ContributorHBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi, Sorry for the mistake.
I tried the same and I only can see the 16bits on the address. These address bits are affected by the setting of "Address width of bursting master" of the PCIe IP. I believe the developer hack the IP and change the address width to 30 instead.
If you need, you can change this by modifying the g3x16_hbm2_avmm_bridge_512_0.ip file.
Search for Address width of Bursting Master and you can change the value to 30.
Frequent ContributorHi, Sorry for the mistake.
I tried the same and I only can see the 16bits on the address. These address bits are affected by the setting of "Address width of bursting master" of the PCIe IP. I believe the developer hack the IP and change the address width to 30 instead.
If you need, you can change this by modifying the g3x16_hbm2_avmm_bridge_512_0.ip file.
Search for Address width of Bursting Master and you can change the value to 30.
Occasional ContributorThanks @BoonT_Intel , it indeed appears that this a some kind of a hack by the developer. Thanks! One a side note, can you refer me to maybe an example design/reference design where I can understand the working/usage of multiple BARS?
