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Altera_Forum's avatar
Altera_Forum
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14 years ago

Hardware -> Nios II big data transfer

Hello, I'm having questions about how to send a big data buffer from my VHDL Hardware component to my Nios II. The problem with this buffer is that its size can vary from 90bits to 2000bit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I see that I won't be able to use the tightly coupled data anyway so, what about writting a FIFO -> Avalon Streaming interface -> SGDMA -> Dual port Onchip memory (S1 on the SGMDA, S2 on the Nios II Data master) -> Nios II (IOWR/IORD direct access) ?

Or should I rather just write an Avalon master interface -> Dual port Onchip memory (S1 on the Avalon Master, S2 on the Nios II Data master) ? (which would be easier I guess)

Thank you again dsl.