Hardware -> Nios II big data transfer

I think all the on-chip memories have 2 ports - so can be accessed by two vhdl components at the same time (with some contraints they can be in different clock domains as well).

Thinks/remembers more... The SOPC builder will only expose the second interface as an Avalon slave (not the raw memory signals). So you either have to write the Avalon master interface (most of which probably doesn't get synthesised for the single-master -> single slave case), or write the Avalon slave -> internal memory login - there are probably lots of copies of that lurking - and put the memory inside your vhdl.

Neither will allow you to use the faster 'tightly coupled data' interface on the cpu.