Altera_Forum
Honored Contributor
13 years agoHard EMIF QSYS generation problem
Hi all,
I'm running Quartus 12.1 on Win 7. I'm trying to migrate my design from "SOPC Builder for Cyclone 4" to "QSYS for Cyclone 5". Because the Altmemphy is no longer suported, I created a UniPhy. But when I generate the design I get the following issue :
Error: s0: Error during execution of "{C:/altera/12.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/altera/12.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: ]2;Altera Nios II EDS 12.1 C:/altera/12.1/quartus/bin/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../cy4c6_sopc_mem_if_ddr2_emif_0_s0_AC_ROM.hex -inst_rom ../cy4c6_sopc_mem_if_ddr2_emif_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_MR0=0101001110011 -DAC_ROM_MR0_CALIB=0101001110011 -DAC_ROM_MR0_DLL_RESET=0101101110011 -DAC_ROM_MR1=0000000000100 -DAC_ROM_MR1_OCD_ENABLE=0001110000100 -DAC_ROM_MR2=0000010000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR= -DAC_ROM_MR0_DLL_RESET_MIRR= -DAC_ROM_MR1_MIRR= -DAC_ROM_MR2_MIRR= -DAC_ROM_MR3_MIRR= -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: s0: UniPHY Sequencer Microcode Compiler
I found a post http://alteraforums.net/forum/showthread.php?p=151954 claiming the solution is "edit nios2eds/bin/elf2hex, change first line to# !/bin/bash". But for me, it doesn't work. Does anybody got an idea? Thanks is advance.