Occasional ContributorGXB stuck in calibration: some new issues
Last year I had an issue where my GXB block (included as part of HDMI RX IP) was stuck in calibration: https://community.intel.com/t5/FPGA-Intellectual-Property/Cyclone-10GX-transceiver-calibration-hung/m-p/1192687
I now have a new situation. I was, after an extended battle, able to get the HDMI RX design working. This design consisted purely of two HDMI RX channels running in a Cyclone 10GX. The design worked on both the Cyclone 10GX dev board, as well as our own prototype hardware.
When I incorporate those same HDMI receivers into my full design, running on the same hardware, the transceivers no longer work: they appear to be stuck in calibration again.
The HDMI RX code used is identical between the two designs (it is, literally, the same code, shared between the two quartus projects.) As far as I can tell, all the connectivity between the pins and the HDMI blocks (clocks, resets, and serial connections) are exactly the same between the two designs.
So again: two designs, both incorporating identical HDMI RX blocks connected to the same pins, running on the same hardware: one works, one doesn't. And once again I have no idea how to determine why calibration is not finishing in the GXB block.
In the previous thread, you suggested I work with the GXB example design to see if I can get it working on my hardware. We are past that now; I've had the HDMI working.
Given known working hardware, what should I look at? I feel like there must be a difference between my two projects, but I've checked through them about a thousand times and haven't come up with anything.
HI,
Your Quartus design is complicated and I may need more time to slowly digest it.
Anyway, I have below 2 extra finding to share with you
- Your Quartus design "device and pin option" setting now set config clock source to internal oscillator instead of CLKUSR pin. This is not recommended as per below KDB guideline
- This 2nd finding here could explained why HDMI transceiver channel calibration stuck after you added in "ehive_dual_pd" platform designer that contains PCIe hard IP
- https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2016/why-doesn-t-the-gen3-stratix-v-pcie-hip-start-flow-control-initi.html
- You can try remove PCIe IP design module and rerun testing to check if PCIe IP is the culprit ?
Thanks.
Regards,
dlim
