GXB stuck in calibration: some new issues

Hi,

Np and thanks for detail explanation.

Fundamentally 2 main factor that can corrupt transceiver (XCVR) power up calibration process should be either clock or reset

• For instance, XCVR channel reset control is toggling while XCVR calibration is running half way
• or the clk supply (reflkc or clkusr) is temp lost/disconnect or become noisy due to coupling noise while XCVR calibration is running half way

Question on signal_tap result :

• In ch[0] connected result, ch[0] PLL_locked asserted high is good but why HDMI 5V detect and HPD signal of ch[1] is asserted instead of ch[0] ?
• Same for ch[1] connected result, ch[1] PLL_locked asserted high is good but why HDMI 5V detect and HPD signal of ch[0] is asserted instead of ch[1] ?
• Is HDMI 5V detect and HPD signal connection so how inverted ? Any other HDMI signals that are inverted ?

Some additional debug input :

• You mentioned using 2 HDMI interface design works but after integrating into full system design (DDR, PCIe and QSYS design) failed.
• Can you gradually just add in one additional design interface at a time and rerun test to isolate which design interface added may be causing issue to HDMI Rx ?
• Once isolated which additional design interface/module is causing HDMI failure then you can further debug on the reset and clocking connection/control at your design top level file.
  • Like any clk/PLL sharing between HDMI and the additional design interface/module ? Or potential noise coupling in FPGA internal clock network ? Are they near to each another in Quartus chip planner view ?
  • Are they sharing same reset synchronizer/control design at top level design file ? Or separate reset control ? You can debug using separate reset control to see if it solved the issue ?
  • Did you accidentally reprogram some clk generator chip on your board ?
  • Can you add further delay in your higher application software design in your overall board reset control mechanism ?

Thanks.

Regards,

dlim