Forum Discussion
Occasional ContributorGXB stuck in calibration: some new issues
HI,
Your Quartus design is complicated and I may need more time to slowly digest it.
Anyway, I have below 2 extra finding to share with you
- Your Quartus design "device and pin option" setting now set config clock source to internal oscillator instead of CLKUSR pin. This is not recommended as per below KDB guideline
- This 2nd finding here could explained why HDMI transceiver channel calibration stuck after you added in "ehive_dual_pd" platform designer that contains PCIe hard IP
- https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2016/why-doesn-t-the-gen3-stratix-v-pcie-hip-start-flow-control-initi.html
- You can try remove PCIe IP design module and rerun testing to check if PCIe IP is the culprit ?
Thanks.
Regards,
dlim
Occasional ContributorI apologize my initial question was badly lacking in details. Here's a simplified block diagram:
There are two HDMI RX channels instantiated at the top level, and then a whole bunch of other stuff instantiated in Platform Designer.
If I comment out the Platform Designer instantiation, and its related I/O (PCIe and the DDR3 controllers) and change nothing else, then both HDMI RX channels work correctly, and can fully lock onto incoming video.
If remove the comments and include everything, the HDMI RX channels stop working, despite the fact that they shouldn't (?) be affected by the rest of the stuff. Timing appears similar between the two builds, no obvious differences there.
Here's a Signaltap with Channel 0 connected:
And here's one with Channel 1 connected:
In both cases, all transceivers seem to be stuck in calibration.
Again, with the rest of the design removed, this all works like it's supposed to. I'm at a loss to figure out the mechanism by which the rest of the design is impacting the transceivers.
