Forum Discussion
NWein
Occasional Contributor
Occasional ContributorGXB stuck in calibration: some new issues
Last year I had an issue where my GXB block (included as part of HDMI RX IP) was stuck in calibration: https://community.intel.com/t5/FPGA-Intellectual-Property/Cyclone-10GX-transceiver-calibration-h...
HI,
Your Quartus design is complicated and I may need more time to slowly digest it.
Anyway, I have below 2 extra finding to share with you
- Your Quartus design "device and pin option" setting now set config clock source to internal oscillator instead of CLKUSR pin. This is not recommended as per below KDB guideline
- This 2nd finding here could explained why HDMI transceiver channel calibration stuck after you added in "ehive_dual_pd" platform designer that contains PCIe hard IP
- https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2016/why-doesn-t-the-gen3-stratix-v-pcie-hip-start-flow-control-initi.html
- You can try remove PCIe IP design module and rerun testing to check if PCIe IP is the culprit ?
Thanks.
Regards,
dlim
Deshi_Intel
Regular Contributor
Regular ContributorHi,
Pls help me to understand your problem statement first.
- Are you saying you have 2 designs (HDMI Rx example design and HDMI full design), one works while the other failed ?
- What's the failure symptom here ? rx_cal_busy signal asserted high forever ? pls elaborate
- Does it mean on the same hardware board, you just program HDMI example design sof then it works. Then you switched to program HDMI full design sof then it failed ?
- If this is the case then confirm is Quartus design issue
- It's either due to design connectivity or qsf pin setting issue in your HDMI full design
- or it also could be due to HDMI Rx design integration to full design is not done properly due to whatever reason
- Pls double check your full design connectivity, qsf file, Quartus synthesis and fitter compilation report and compare with HDMI example design to find for any abnormality
- Also have you tried regenerate the HDMI IP and NativePHY IP again in HDMI full design ?
- Does it mean on the same hardware board, you just program HDMI example design sof then it works. Then you switched to program HDMI full design sof then it failed ?
- You also mentioned two HDMI RX channels running in a Cyclone 10GX
- Does it means you have 2 HDMI Rx IP in Cyclone 10GX ?
- Which HDMI Rx IP is facing XCVR calibration issue ? Just one or both IP ?
- Which transceiver channel is facing calibration issue ?
Thanks.
Regards,
dlim
