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mjj67's avatar
mjj67
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22 days ago

GTS JESD204C IP Evaluation Mode not working

Using Quartus Pro 25.3 I can't generate time limited sof for GTS JESD204C. I have reviewed Licensing 'know-How' Guild. I found and corrected an issue with the LM_LICENSE_FILE variable. I have verifie...
Jesd
mjj67's avatar
mjj67
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21 days ago

Hello,

Thank you for the reply. I was in the process of installing 26.1 Pro when you replied. I successfully installed Quartus Pro 26.1 and verified SHA1 was good on the download. I opened my project and instead of using "Upgrade IP" I chose to do this manually via Platform Designer. Both qsys files failed to generate with exit code 3.

I documented all of the setting I used when I created this project and have decided to recreate this from scratch under 26.1 to see what happens. I'll report back when finished to let you know how it turns out.

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mjj67
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21 days ago

I confirm that recreating the GTS JESD204C example design from scratch under Quartus Pro 26.1 produced a time-limited sof file; however, timing requirements not met. This could be related to the setting I used in the IP.

Additional notes:

  • When I generated the example designe it ends with Error: Failed to generate example_design
  • Close Plaform Designer and select NO for "Recent changes have not been generated. Generate now?"
  • Under Quartus goto File > Open Project
  • Navigate to the generated project <original project path> jesd204c_gts_0_example_design > ed > quartus > jesd204c_gts_ed_rx_tx.qpf
  • If asked to close current project, Click Yes
  • Open Platform Designer
  • For Platform Designer system, Navigate to <original project path>  jesd204c_gts_0_example_design > ed > rtl > du > j204c_gts_rx_tx_ip.qsys (this is a sub-system)
  • For "Open System Completed", Click Close
  • Click "Generate HDL..."
  • I checked "Include Altera attributes in generated HDL to detect interfaces in Node Finder and RTL Analyzer"
  • Click Gernerate
  • I got "Generate: completed with warnings." Click Close
  • Platform Designer, Open File
  • For Platform Designer system, Navigate to <original project path>  jesd204c_gts_0_example_design > ed > rtl > du > j204c_gts_rx_tx_ss.qsys (this is the top-level qsys)
  • Click "Generate HDL..."
  • I got "Generate: completed with warnings." Click Close
  • Close Platform Designer
  • Under Quartus, Compile
  • I got "Full Compilation was successful (22 warnings)"
  • Using windows file explorer I confirmed that jesd204c_gts_rx_tx_time_limited.sof was created.
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    19 days ago

    Hi,

     

    Thank you for the update. I’m glad to hear that the SOF issue has been resolved with Quartus 26.1, and I appreciate you sharing the additional notes on the workaround.

     

    Could you please share the detailed steps to reproduce the error “Error: Failed to generate example_design”? I’d like to replicate the issue on my side and investigate it further.

     

    Please let me know if you have any questions or concerns. Thank you.