Full Rate Mode in DDR2 HP Controller

All timing diagrams in HP controller manual are for native mode, full rate, as said at page 4-11.

Hello, thanks for responding to my post. I looked at page 4-11 and I only see timing diagrams for

I refer to ddr & ddr2 sdram high-performance controller v7.2 user guide

Hello, now I see the disconnect. I'm using DDR & DDR2 SDRAM High-Performance Controller v8.0 User Guide documentation which is different than 7.2. Do you think there is a difference between 7.2 and 8.0? Looking at the timing diagrams briefly there appears some difference. Could you you at the 8.0 doc and comment on what they have when you have some free time.

Looking closer at 7.2 I see that the local_addr is broken down into other signals this is not done in 8.0, do you know where I can find where it breaks that down. I've looked through the verilog code but I can't find that information.

I downloaded Quartus V8.0, but didn't yet install it. I don't expect, that the basic decoding scheme of local addresses has been changed with V8.0 HP controller, cause the mapping is almost obvious and doesn't give much room for alternatives to my opinion. But I may be wrong. I also wasn't aware of big differences in local bus interface timing between half and full rate, except for the latency when measured in clock cycles.