FrameBuffer: A few easy questions..

I'm porting code that used an old, and very different frame buffer from 2010 IP. I'm having a hard time figuring out which signals map to which ports on Altera's new Frame buffer. See below: (The bigger project takes pixel data from a CMOS board camera and displays it using VGA. The next step will be using the SDRAM instead of the limited FPGA memory using a controller I already have.)

Inst_frame_buffer : frame_buffer PORT MAP(
            rdaddress => rdaddress,     --    IN std_logic_vector(18 downto 0);
            rdclock   => clk_vga,       --    IN std_logic;
            q         => rddata,        --    OUT std_logic_vector(11 downto 0)     
            wrclock   => ov7670_pclk,   --    IN std_logic;
            wraddress => wraddress(18 downto 0), --    IN std_logic_vector(18 downto 0);
            data      => wrdata,        --    IN std_logic_vector(11 downto 0);
            wren      => wren           --    IN std_logic;     
        );

Inst_frame_buffer : frame_buffer PORT MAP(
        clock                                        => ??        --:  IN STD_LOGIC;
        reset                                        => ??        --:  IN STD_LOGIC;
        din_ready                                => ??        --:  OUT STD_LOGIC;
        din_valid                                    => ??        --:  IN STD_LOGIC;
        din_data                                    => ??        --:  IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        din_startofpacket                        => ??        --:  IN STD_LOGIC;
        din_endofpacket                        => ??        --:  IN STD_LOGIC;
        dout_ready                                => ??        --:  IN STD_LOGIC;
        dout_valid                                => ??        --:  OUT STD_LOGIC;
        dout_data                                => ??        --:  OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
        dout_startofpacket                    => ??        --:  OUT STD_LOGIC;
        dout_endofpacket                    => ??        --:  OUT STD_LOGIC;
        read_master_av_address            => ??        --:  OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        read_master_av_read                => ??        --:  OUT STD_LOGIC;
        read_master_av_waitrequest        => ??        --:  IN STD_LOGIC;
        read_master_av_readdatavalid    => ??        --:  IN STD_LOGIC;
        read_master_av_readdata            => ??        --:  IN STD_LOGIC_VECTOR (63 DOWNTO 0);
        read_master_av_burstcount        => ??        --:  OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
        write_master_av_address            => ??        --:  OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        write_master_av_write                => ??        --:  OUT STD_LOGIC;
        write_master_av_writedata        => ??        --:  OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
        write_master_av_waitrequest        => ??        --:  IN STD_LOGIC;
        write_master_av_burstcount        => ??        --:  OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
    );