Hi,
Some intresting observation, test pattern (1280X720p@50Hz) running with external clock(camera clock 74.25MHz) works fine so from this test i concluded that there is no bandwidth issue with this resolution.
I looked at the camera DVI output data enable signal, there i found that the the TI DVI receiver was generating data enable for more than 1280 pixel value, which i fixed it by writing a samll code in FPGA and woooow the result was clear picture...:)
know i am trying to connect 1920X1080i to see wether cyclone III starter board has bandwidth to support this resolution