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IMura's avatar
IMura
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

fPLL Arria10 powerdown does nothing

Hello, I instantiated an fPLL in the transceiver mode as I am using with the JESD204b IP. I noticed that the fPLL can't seem to be "reset" once the FPGA has been configured. Looking at the signalta...
  • CheepinC_altera's avatar
    CheepinC_altera
    4 years ago

    Hi,


    Thanks for your update. Regarding your latest observation on the PLL powerdown, as I check with the registermap, there seems to be no issue with the registers that you are accessing.


    Just to check with you on the following:


    1. Just wonder if the "Enable capability registers" and "Enable control and status registers" under the Optional Reconfiguration Logic tab are checked in the fPLL IP core during instantiation?


    2. If after performing #1, similar problem persists. Would you mind to help performing a Modelsim simulation to check on the functional behavior to see if the observation is consistent?


    Please let me know if there is any concern. Thank you.


CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Thanks for your update. Glad that you have managed to resolve the problem.


I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.