Forum Discussion
Occasional ContributorfPLL Arria10 powerdown does nothing
Hi,
Thanks for your update. Regarding your latest observation on the PLL powerdown, as I check with the registermap, there seems to be no issue with the registers that you are accessing.
Just to check with you on the following:
1. Just wonder if the "Enable capability registers" and "Enable control and status registers" under the Optional Reconfiguration Logic tab are checked in the fPLL IP core during instantiation?
2. If after performing #1, similar problem persists. Would you mind to help performing a Modelsim simulation to check on the functional behavior to see if the observation is consistent?
Please let me know if there is any concern. Thank you.
Regular ContributorThanks for your update. Glad that you have managed to resolve the addressing and recalibrate your fPLL.
Regarding your latest inquiry on the register offset, as I look at the register map, seems like the address matches the user guide. Not sure if I have missed out anything. Thank you.
Occasional ContributorAmongst the things that don't seem to correlate :
in the register map, at offset 0x280, bit [0] we should be able to read the 'pll_locked'. When I read at this offset, it always returns 0 even when the fPLL is clearly locked from the signaltap output.
at offset 0x2E0, if I wrote '3', I should be able to powerdown the fPLL and. However, looking at the signaltap output, this powerdown doesn't work (the locked signal is still '1').
Thanks
