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IMura's avatar
IMura
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

fPLL Arria10 powerdown does nothing

Hello, I instantiated an fPLL in the transceiver mode as I am using with the JESD204b IP. I noticed that the fPLL can't seem to be "reset" once the FPGA has been configured. Looking at the signalta...
  • CheepinC_altera's avatar
    CheepinC_altera
    4 years ago

    Hi,


    Thanks for your update. Regarding your latest observation on the PLL powerdown, as I check with the registermap, there seems to be no issue with the registers that you are accessing.


    Just to check with you on the following:


    1. Just wonder if the "Enable capability registers" and "Enable control and status registers" under the Optional Reconfiguration Logic tab are checked in the fPLL IP core during instantiation?


    2. If after performing #1, similar problem persists. Would you mind to help performing a Modelsim simulation to check on the functional behavior to see if the observation is consistent?


    Please let me know if there is any concern. Thank you.


CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Sorry for the delay. Yes, you are right. You need to enable the dynamic reconfiguration and manual write to the AVMM registers. You may refer to "Fractional PLL Recalibration" in the A10 XCVR PHY user guide for further details on the registers to write to.


Please let me know if there is any concern. Thank you.


  • IMura's avatar
    IMura
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi,

    I tried following the "7.5.2. Fractional PLL Recalibration " in the A10 XCVR PHY UG but it's very confusing.

    First of all, by enabling the 'dynamic reconfiguration' on the fPLL, there is the avl mm bus with 10-bit address and 32-bit data. Are the addresses byte addresses or word addresses?

    Because looking at the a10_registermap.xlsx (below is the excerpt), the addresses are not multiple of 4 which makes me think that they are word addresses? I can't seem to read and write to the fPLL and see anything. for example, looking at the signaltap locked output, i know that the fpll is locked but reading the "pll_locked" register, it just stays '0'.

    How can I access these registers correctly then?

    Thanks

    • IMura's avatar
      IMura
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hi again,

      I finally figured out that the "7.5.2. Fractional PLL Recalibration " in the A10 XCVR PHY UG steps use byte addressing and I seem to be able to recalibrate the fPLL (the cal_is_busy signal can finally be toggled).

      However I still don't know why the a10_registermap.xlsx doesn't have the same offset addresses for the fPLL. Why aren't they the same?

      Thanks