Forum Discussion
Occasional ContributorfPLL Arria10 powerdown does nothing
Hi,
Thanks for your update. Regarding your latest observation on the PLL powerdown, as I check with the registermap, there seems to be no issue with the registers that you are accessing.
Just to check with you on the following:
1. Just wonder if the "Enable capability registers" and "Enable control and status registers" under the Optional Reconfiguration Logic tab are checked in the fPLL IP core during instantiation?
2. If after performing #1, similar problem persists. Would you mind to help performing a Modelsim simulation to check on the functional behavior to see if the observation is consistent?
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
Sorry for the delay. This case has just been routed to me.
As I understand it, your latest problem is related to fPLL not able to lock when there is no refclk present during device power up. For your information, in this case, you would need to perform the fPLL recalibration because the power up calibration cannot run correctly without refclk present during device power up.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Occasional ContributorHi,
Thank you for your response.
Yes, the latest problem is exactly that. My current setup relies on a clock chip that needs to be configured first once the FPGA is loaded so having the transceiver ref clock running before the FPGA image is uploaded is quite complicated.
So to solve this problem, I would need to do the fPLL recalibration : To do this, do I need to enable the dynamic reconfiguration? Does it mean that I will have to manually write to the registers through, I guess, the avalon MM bus of the dynamic reconfiguration?
Thanks.
Regards,
